/********************************** (C) COPYRIGHT *******************************
 * File Name          : ch32v20x_tim5.c
 * Author             : ÂÞ³É
 * Version            : V1.0.0
 * Date               : 2021/06/06
 * Description        : This file provides all the TIM firmware functions.
*******************************************************************************/
#include "ch32v20x_tim5.h"
#include "ch32v20x_rcc.h"

/* TIM registers bit mask */
#define TIM5_SMCFGR_ETR_Mask    ((uint16_t)0x00FF)
#define TIM5_CHCTLR_Offset      ((uint16_t)0x0018)
#define TIM5_CCER_CCE_Set       ((uint16_t)0x0001)
#define TIM5_CCER_CCNE_Set      ((uint16_t)0x0004)

static void TI1_Config(uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter);
static void TI2_Config(uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter);
static void TI3_Config(uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter);
static void TI4_Config(uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter);

/*********************************************************************
 * @fn      TIM5_DeInit
 *
 * @brief   Deinitializes the TIM5 peripheral registers to their default
 *        reset values.
 *
 * @param   none
 *
 * @return  none
 */
void TIM5_DeInit(void)
{
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
}

/*********************************************************************
 * @fn      TIM5_TimeBaseInit
 *
 * @brief   Initializes the TIM5 Time Base Unit peripheral according to
 *        the specified parameters in the TIM_TimeBaseInitStruct.
 *
 * @param TIM_TimeBaseInitStruct - pointer to a TIM5_TimeBaseInitTypeDef
 *        structure.
 *
 * @return  none
 */
void TIM5_TimeBaseInit(TIM5_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
{
    uint16_t tmpcr1 = 0;

    tmpcr1 = TIM5->CTLR1;
    tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS)));
    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;

    tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD));
    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;

    TIM5->CTLR1 = tmpcr1;
    TIM5->ATRLR_R32 = TIM_TimeBaseInitStruct->TIM_Period;
    TIM5->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;

    TIM5->SWEVGR = TIM_PSCReloadMode_Immediate;
}

/*********************************************************************
 * @fn      TIM5_OC1Init
 *
 * @brief   Initializes the TIM5 Channel1 according to the specified
 *        parameters in the TIM_OCInitStruct.
 *
 * @param   TIM_OCInitStruct - pointer to a TIM5_OCInitTypeDef structure.
 *
 * @return  none
 */
void TIM5_OC1Init(TIM5_OCInitTypeDef *TIM_OCInitStruct)
{
    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;

    TIM5->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E);
    tmpccer = TIM5->CCER;
    tmpcr2 = TIM5->CTLR2;
    tmpccmrx = TIM5->CHCTLR1;
    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M));
    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S));
    tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P));
    tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
    tmpccer |= TIM_OCInitStruct->TIM_OutputState;

    TIM5->CTLR2 = tmpcr2;
    TIM5->CHCTLR1 = tmpccmrx;
    TIM5->CH1CVR_R32 = TIM_OCInitStruct->TIM_Pulse;
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TIM5_OC2Init
 *
 * @brief   Initializes the TIM5 Channel2 according to the specified
 *        parameters in the TIM_OCInitStruct.
 *
 * @param   TIM_OCInitStruct - pointer to a TIM5_OCInitTypeDef structure.
 *
 * @return  none
 */
void TIM5_OC2Init(TIM5_OCInitTypeDef *TIM_OCInitStruct)
{
    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;

    TIM5->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E));
    tmpccer = TIM5->CCER;
    tmpcr2 = TIM5->CTLR2;
    tmpccmrx = TIM5->CHCTLR1;
    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M));
    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S));
    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P));
    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);

    TIM5->CTLR2 = tmpcr2;
    TIM5->CHCTLR1 = tmpccmrx;
    TIM5->CH2CVR_R32 = TIM_OCInitStruct->TIM_Pulse;
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TIM5_OC3Init
 *
 * @brief   Initializes the TIM5 Channel3 according to the specified
 *        parameters in the TIM_OCInitStruct.
 *
 * @param   TIM_OCInitStruct - pointer to a TIM5_OCInitTypeDef structure.
 *
 * @return  none
 */
void TIM5_OC3Init(TIM5_OCInitTypeDef *TIM_OCInitStruct)
{
    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;

    TIM5->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E));
    tmpccer = TIM5->CCER;
    tmpcr2 = TIM5->CTLR2;
    tmpccmrx = TIM5->CHCTLR2;
    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M));
    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S));
    tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P));
    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);

    TIM5->CTLR2 = tmpcr2;
    TIM5->CHCTLR2 = tmpccmrx;
    TIM5->CH3CVR_R32 = TIM_OCInitStruct->TIM_Pulse;
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TIM5_OC4Init
 *
 * @brief   Initializes the TIM5 Channel4 according to the specified
 *        parameters in the TIM_OCInitStruct.
 *
 * @param   TIM_OCInitStruct - pointer to a TIM5_OCInitTypeDef structure.
 *
 * @return  none
 */
void TIM5_OC4Init(TIM5_OCInitTypeDef *TIM_OCInitStruct)
{
    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;

    TIM5->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E));
    tmpccer = TIM5->CCER;
    tmpcr2 = TIM5->CTLR2;
    tmpccmrx = TIM5->CHCTLR2;
    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M));
    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S));
    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P));
    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);

    TIM5->CTLR2 = tmpcr2;
    TIM5->CHCTLR2 = tmpccmrx;
    TIM5->CH4CVR_R32 = TIM_OCInitStruct->TIM_Pulse;
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TIM5_ICInit
 *
 * @brief   IInitializes the TIM peripheral according to the specified
 *        parameters in the TIM_ICInitStruct.
 * @param   TIM5 - where x can be 1 to 4 to select the TIM peripheral.
 *          TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure.
 *
 * @return  none
 */
void TIM5_ICInit(TIM5_ICInitTypeDef *TIM_ICInitStruct)
{
    if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
    {
        TI1_Config(TIM_ICInitStruct->TIM_ICPolarity,
                   TIM_ICInitStruct->TIM_ICSelection,
                   TIM_ICInitStruct->TIM_ICFilter);
        TIM5_SetIC1Prescaler(TIM_ICInitStruct->TIM_ICPrescaler);
    }
    else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
    {
        TI2_Config(TIM_ICInitStruct->TIM_ICPolarity,
                   TIM_ICInitStruct->TIM_ICSelection,
                   TIM_ICInitStruct->TIM_ICFilter);
        TIM5_SetIC2Prescaler(TIM_ICInitStruct->TIM_ICPrescaler);
    }
    else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
    {
        TI3_Config(TIM_ICInitStruct->TIM_ICPolarity,
                   TIM_ICInitStruct->TIM_ICSelection,
                   TIM_ICInitStruct->TIM_ICFilter);
        TIM5_SetIC3Prescaler(TIM_ICInitStruct->TIM_ICPrescaler);
    }
    else
    {
        TI4_Config(TIM_ICInitStruct->TIM_ICPolarity,
                   TIM_ICInitStruct->TIM_ICSelection,
                   TIM_ICInitStruct->TIM_ICFilter);
        TIM5_SetIC4Prescaler(TIM_ICInitStruct->TIM_ICPrescaler);
    }
}

/*********************************************************************
 * @fn      TIM5_PWMIConfig
 *
 * @brief   Configures the TIM peripheral according to the specified
 *        parameters in the TIM_ICInitStruct to measure an external
 *        PWM signal.
 *
 * @param   TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure.
 *
 * @return  none
 */
void TIM5_PWMIConfig(TIM5_ICInitTypeDef *TIM_ICInitStruct)
{
    uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
    uint16_t icoppositeselection = TIM_ICSelection_DirectTI;

    if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
    {
        icoppositepolarity = TIM_ICPolarity_Falling;
    }
    else
    {
        icoppositepolarity = TIM_ICPolarity_Rising;
    }

    if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
    {
        icoppositeselection = TIM_ICSelection_IndirectTI;
    }
    else
    {
        icoppositeselection = TIM_ICSelection_DirectTI;
    }

    if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
    {
        TI1_Config(TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
                   TIM_ICInitStruct->TIM_ICFilter);
        TIM5_SetIC1Prescaler(TIM_ICInitStruct->TIM_ICPrescaler);
        TI2_Config(icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
        TIM5_SetIC2Prescaler(TIM_ICInitStruct->TIM_ICPrescaler);
    }
    else
    {
        TI2_Config(TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
                   TIM_ICInitStruct->TIM_ICFilter);
        TIM5_SetIC2Prescaler(TIM_ICInitStruct->TIM_ICPrescaler);
        TI1_Config(icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
        TIM5_SetIC1Prescaler(TIM_ICInitStruct->TIM_ICPrescaler);
    }
}

/*********************************************************************
 * @fn      TIM5_BDTRConfig
 *
 * @brief   Configures the: Break feature, dead time, Lock level, the OSSI,
 *      the OSSR State and the AOE(automatic output enable).
 *
 * @param   TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure.
 *
 * @return  none
 */
void TIM5_BDTRConfig(TIM5_BDTRInitTypeDef *TIM_BDTRInitStruct)
{
    TIM5->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
                 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
                 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
                 TIM_BDTRInitStruct->TIM_AutomaticOutput;
}

/*********************************************************************
 * @fn      TIM5_TimeBaseStructInit
 *
 * @brief   Fills each TIM_TimeBaseInitStruct member with its default value.
 *
 * @param   TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure.
 *
 * @return  none
 */
void TIM5_TimeBaseStructInit(TIM5_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
{
    TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
    TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
    TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
    TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
    TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
}

/*********************************************************************
 * @fn      TIM5_OCStructInit
 *
 * @brief   Fills each TIM_OCInitStruct member with its default value.
 *
 * @param   TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
 *
 * @return  none
 */
void TIM5_OCStructInit(TIM5_OCInitTypeDef *TIM_OCInitStruct)
{
    TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
    TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
    TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
    TIM_OCInitStruct->TIM_Pulse = 0x0000;
    TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
    TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
    TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
    TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
}

/*********************************************************************
 * @fn      TIM5_ICStructInit
 *
 * @brief   Fills each TIM_ICInitStruct member with its default value.
 *
 * @param   TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure.
 *
 * @return  none
 */
void TIM5_ICStructInit(TIM5_ICInitTypeDef *TIM_ICInitStruct)
{
    TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
    TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
    TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
    TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
    TIM_ICInitStruct->TIM_ICFilter = 0x00;
}

/*********************************************************************
 * @fn      TIM5_BDTRStructInit
 *
 * @brief   Fills each TIM_BDTRInitStruct member with its default value.
 *
 * @param   TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure.
 *
 * @return  none
 */
void TIM5_BDTRStructInit(TIM5_BDTRInitTypeDef *TIM_BDTRInitStruct)
{
    TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
    TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
    TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
    TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
    TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
    TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
    TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
}

/*********************************************************************
 * @fn      TIM5_Cmd
 *
 * @brief   Enables or disables the specified TIM peripheral.
 *
 * @param   NewState - ENABLE or DISABLE.
 *
 * @return  none
 */
void TIM5_Cmd(FunctionalState NewState)
{
    if(NewState != DISABLE)
    {
        TIM5->CTLR1 |= TIM_CEN;
    }
    else
    {
        TIM5->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN));
    }
}

/*********************************************************************
 * @fn      TIM5_CtrlPWMOutputs
 *
 * @brief   Enables or disables the TIM peripheral Main Outputs.
 *
 * @param   NewState - ENABLE or DISABLE.
 *
 * @return  none
 */
void TIM5_CtrlPWMOutputs(FunctionalState NewState)
{
    if(NewState != DISABLE)
    {
        TIM5->BDTR |= TIM_MOE;
    }
    else
    {
        TIM5->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE));
    }
}

/*********************************************************************
 * @fn      TIM5_ITConfig
 *
 * @brief   Enables or disables the specified TIM interrupts.
 *
 * @param   TIM_IT - specifies the TIM interrupts sources to be enabled or disabled.
 *            TIM_IT_Update - TIM update Interrupt source.
 *            TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source.
 *            TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source
 *            TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source.
 *            TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source.
 *            TIM_IT_COM - TIM Commutation Interrupt source.
 *            TIM_IT_Trigger - TIM Trigger Interrupt source.
 *            TIM_IT_Break - TIM Break Interrupt source.
 *          NewState - ENABLE or DISABLE.
 *
 * @return  none
 */
void TIM5_ITConfig(uint16_t TIM_IT, FunctionalState NewState)
{
    if(NewState != DISABLE)
    {
        TIM5->DMAINTENR |= TIM_IT;
    }
    else
    {
        TIM5->DMAINTENR &= (uint16_t)~TIM_IT;
    }
}

/*******************************************************************************
 * @fn             TIM_GenerateEvent
 *
 * @brief          Configures the TIM5 event to be generate by software.
 *
 * @param          TIM_EventSource: specifies the event source.
 *                 TIM_EventSource_Update: Timer update Event source.
 *                 TIM_EventSource_CC1: Timer Capture Compare 1 Event source.
 *                 TIM_EventSource_CC2: Timer Capture Compare 2 Event source.
 *                 TIM_EventSource_CC3: Timer Capture Compare 3 Event source.
 *                 TIM_EventSource_CC4: Timer Capture Compare 4 Event source.
 *                 TIM_EventSource_COM: Timer COM event source.
 *                 TIM_EventSource_Trigger: Timer Trigger Event source.
 *                 TIM_EventSource_Break: Timer Break event source.
 *
 * @return None
 */
void TIM5_GenerateEvent(uint16_t TIM_EventSource)
{
    TIM5->SWEVGR = TIM_EventSource;
}

/*********************************************************************
 * @fn      TIM5_DMAConfig
 *
 * @brief   Configures the TIM5's DMA interface.
 *
 * @param   TIM_DMABase: DMA Base address.
 *            TIM_DMABase_CR.
 *            TIM_DMABase_CR2.
 *            TIM_DMABase_SMCR.
 *            TIM_DMABase_DIER.
 *            TIM1_DMABase_SR.
 *            TIM_DMABase_EGR.
 *            TIM_DMABase_CCMR1.
 *            TIM_DMABase_CCMR2.
 *            TIM_DMABase_CCER.
 *            TIM_DMABase_CNT.
 *            TIM_DMABase_PSC.
 *            TIM_DMABase_CCR1.
 *            TIM_DMABase_CCR2.
 *            TIM_DMABase_CCR3.
 *            TIM_DMABase_CCR4.
 *            TIM_DMABase_BDTR.
 *            TIM_DMABase_DCR.
 *          TIM_DMABurstLength - DMA Burst length.
 *            TIM_DMABurstLength_1Transfer.
 *            TIM_DMABurstLength_18Transfers.
 *
 * @return  none
 */
void TIM5_DMAConfig(uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
{
    TIM5->DMACFGR = TIM_DMABase | TIM_DMABurstLength;
}

/*********************************************************************
 * @fn      TIM5_DMACmd
 *
 * @brief   Enables or disables the TIM5's DMA Requests.
 *
 * @param   TIM_DMASource - specifies the DMA Request sources.
 *            TIM_DMA_Update - TIM update Interrupt source.
 *            TIM_DMA_CC1 - TIM Capture Compare 1 DMA source.
 *            TIM_DMA_CC2 - TIM Capture Compare 2 DMA source.
 *            TIM_DMA_CC3 - TIM Capture Compare 3 DMA source.
 *            TIM_DMA_CC4 - TIM Capture Compare 4 DMA source.
 *            TIM_DMA_COM - TIM Commutation DMA source.
 *            TIM_DMA_Trigger - TIM Trigger DMA source.
 *          NewState - ENABLE or DISABLE.
 *
 * @return  none
 */
void TIM5_DMACmd(uint16_t TIM_DMASource, FunctionalState NewState)
{
    if(NewState != DISABLE)
    {
        TIM5->DMAINTENR |= TIM_DMASource;
    }
    else
    {
        TIM5->DMAINTENR &= (uint16_t)~TIM_DMASource;
    }
}

/*********************************************************************
 * @fn      TIM5_InternalClockConfig
 *
 * @brief   Configures the TIM5 internal Clock.
 *
 * @param   TIM5 - where x can be 1 to 4 to select the TIM peripheral.
 *
 * @return  none
 */
void TIM5_InternalClockConfig(void)
{
    TIM5->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS));
}

/*********************************************************************
 * @fn      TIM5_ITRxExternalClockConfig
 *
 * @brief   Configures the TIM5 Internal Trigger as External Clock.
 *
 * @param   TIM_InputTriggerSource: Trigger source.
 *            TIM_TS_ITR0 - Internal Trigger 0.
 *            TIM_TS_ITR1 - Internal Trigger 1.
 *            TIM_TS_ITR2 - Internal Trigger 2.
 *            TIM_TS_ITR3 - Internal Trigger 3.
 *
 * @return  none
 */
void TIM5_ITRxExternalClockConfig(uint16_t TIM_InputTriggerSource)
{
    TIM_SelectInputTrigger(TIM5, TIM_InputTriggerSource);
    TIM5->SMCFGR |= TIM_SlaveMode_External1;
}

/*********************************************************************
 * @fn      TIM5_TIxExternalClockConfig
 *
 * @brief   Configures the TIM5 Trigger as External Clock.
 *
 * @param   TIM_TIxExternalCLKSource - Trigger source.
 *            TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector.
 *            TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1.
 *            TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2.
 *          TIM_ICPolarity - specifies the TIx Polarity.
 *             TIM_ICPolarity_Rising.
 *             TIM_ICPolarity_Falling.
 *             TIM_DMA_COM - TIM Commutation DMA source.
 *             TIM_DMA_Trigger - TIM Trigger DMA source.
 *          ICFilter - specifies the filter value.
 *             This parameter must be a value between 0x0 and 0xF.
 *
 * @return  none
 */
void TIM5_TIxExternalClockConfig(uint16_t TIM_TIxExternalCLKSource,
                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
{
    if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
    {
        TI2_Config(TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
    }
    else
    {
        TI1_Config(TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
    }

    TIM_SelectInputTrigger(TIM5, TIM_TIxExternalCLKSource);
    TIM5->SMCFGR |= TIM_SlaveMode_External1;
}

/*********************************************************************
 * @fn      TIM5_ETRClockMode1Config
 *
 * @brief   Configures the External clock Mode1.
 *
 * @param   TIM_ExtTRGPrescaler - The external Trigger Prescaler.
 *            TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF.
 *            TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2.
 *            TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4.
 *            TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8.
 *          TIM_ExtTRGPolarity - The external Trigger Polarity.
 *            TIM_ExtTRGPolarity_Inverted - active low or falling edge active.
 *            TIM_ExtTRGPolarity_NonInverted - active high or rising edge active.
 *          ExtTRGFilter - External Trigger Filter.
 *             This parameter must be a value between 0x0 and 0xF.
 *
 * @return  none
 */
void TIM5_ETRClockMode1Config(uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
                             uint16_t ExtTRGFilter)
{
    uint16_t tmpsmcr = 0;

    TIM_ETRConfig(TIM5, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
    tmpsmcr = TIM5->SMCFGR;
    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS));
    tmpsmcr |= TIM_SlaveMode_External1;
    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS));
    tmpsmcr |= TIM_TS_ETRF;
    TIM5->SMCFGR = tmpsmcr;
}

/*********************************************************************
 * @fn      TIM5_ETRClockMode2Config
 *
 * @brief   Configures the External clock Mode2.
 *
 * @param   TIM_ExtTRGPrescaler - The external Trigger Prescaler.
 *            TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF.
 *            TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2.
 *            TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4.
 *            TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8.
 *          TIM_ExtTRGPolarity - The external Trigger Polarity.
 *            TIM_ExtTRGPolarity_Inverted - active low or falling edge active.
 *            TIM_ExtTRGPolarity_NonInverted - active high or rising edge active.
 *          ExtTRGFilter - External Trigger Filter.
 *            This parameter must be a value between 0x0 and 0xF.
 *
 * @return  none
 */
void TIM5_ETRClockMode2Config(uint16_t TIM_ExtTRGPrescaler,
                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
{
    TIM_ETRConfig(TIM5, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
    TIM5->SMCFGR |= TIM_ECE;
}

/*********************************************************************
 * @fn      TIM5_ETRConfig
 *
 * @brief   Configures the TIM5 External Trigger (ETR).
 *
 * @param   TIM_ExtTRGPrescaler - The external Trigger Prescaler.
 *            TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF.
 *            TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2.
 *            TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4.
 *            TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8.
 *          TIM_ExtTRGPolarity - The external Trigger Polarity.
 *            TIM_ExtTRGPolarity_Inverted - active low or falling edge active.
 *            TIM_ExtTRGPolarity_NonInverted - active high or rising edge active.
 *          ExtTRGFilter - External Trigger Filter.
 *            This parameter must be a value between 0x0 and 0xF.
 *
 * @return  none
 */
void TIM5_ETRConfig(uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
                   uint16_t ExtTRGFilter)
{
    uint16_t tmpsmcr = 0;

    tmpsmcr = TIM5->SMCFGR;
    tmpsmcr &= TIM5_SMCFGR_ETR_Mask;
    tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
    TIM5->SMCFGR = tmpsmcr;
}

/*********************************************************************
 * @fn      TIM5_PrescalerConfig
 *
 * @brief   Configures the TIM5 Prescaler.
 *
 * @param   Prescaler - specifies the Prescaler Register value.
 *          TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode.
 *            TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode.
 *            TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event.
 *            TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately.
 *
 * @return  none
 */
void TIM5_PrescalerConfig(uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
{
    TIM5->PSC = Prescaler;
    TIM5->SWEVGR = TIM_PSCReloadMode;
}

/*********************************************************************
 * @fn      TIM5_CounterModeConfig
 *
 * @brief   Specifies the TIM5 Counter Mode to be used.
 *
 * @param   TIM_CounterMode - specifies the Counter Mode to be used.
 *            TIM_CounterMode_Up - TIM Up Counting Mode.
 *            TIM_CounterMode_Down - TIM Down Counting Mode.
 *            TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1.
 *            TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2.
 *            TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3.
 *
 * @return  none
 */
void TIM5_CounterModeConfig(uint16_t TIM_CounterMode)
{
    uint16_t tmpcr1 = 0;

    tmpcr1 = TIM5->CTLR1;
    tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS)));
    tmpcr1 |= TIM_CounterMode;
    TIM5->CTLR1 = tmpcr1;
}

/*********************************************************************
 * @fn      TIM5_SelectInputTrigger
 *
 * @brief   Selects the Input Trigger source.
 *
 * @param   TIM_InputTriggerSource - The Input Trigger source.
 *            TIM_TS_ITR0 - Internal Trigger 0.
 *            TIM_TS_ITR1 - Internal Trigger 1.
 *            TIM_TS_ITR2 - Internal Trigger 2.
 *            TIM_TS_ITR3 - Internal Trigger 3.
 *            TIM_TS_TI1F_ED - TI1 Edge Detector.
 *            TIM_TS_TI1FP1 - Filtered Timer Input 1.
 *            TIM_TS_TI2FP2 - Filtered Timer Input 2.
 *            TIM_TS_ETRF - External Trigger input.
 *
 * @return  none
 */
void TIM5_SelectInputTrigger(uint16_t TIM_InputTriggerSource)
{
    uint16_t tmpsmcr = 0;

    tmpsmcr = TIM5->SMCFGR;
    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS));
    tmpsmcr |= TIM_InputTriggerSource;
    TIM5->SMCFGR = tmpsmcr;
}

/*********************************************************************
 * @fn      TIM_EncoderInterfaceConfig
 *
 * @brief   Configures the TIM5 Encoder Interface.
 *
 * @param   TIM_EncoderMode - specifies the TIM5 Encoder Mode.
 *            TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending
 *        on TI2FP2 level.
 *            TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending
 *        on TI1FP1 level.
 *            TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and
 *        TI2FP2 edges depending.
 *          TIM_IC1Polarity - specifies the IC1 Polarity.
 *            TIM_ICPolarity_Falling - IC Falling edge.
 *            TTIM_ICPolarity_Rising - IC Rising edge.
 *          TIM_IC2Polarity - specifies the IC2 Polarity.
 *            TIM_ICPolarity_Falling - IC Falling edge.
 *            TIM_ICPolarity_Rising - IC Rising edge.
 *
 * @return  none
 */
void TIM5_EncoderInterfaceConfig(uint16_t TIM_EncoderMode,
                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
{
    uint16_t tmpsmcr = 0;
    uint16_t tmpccmr1 = 0;
    uint16_t tmpccer = 0;

    tmpsmcr = TIM5->SMCFGR;
    tmpccmr1 = TIM5->CHCTLR1;
    tmpccer = TIM5->CCER;
    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS));
    tmpsmcr |= TIM_EncoderMode;
    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S)));
    tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0;
    tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P)));
    tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
    TIM5->SMCFGR = tmpsmcr;
    TIM5->CHCTLR1 = tmpccmr1;
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TIM5_ForcedOC1Config
 *
 * @brief   Forces the TIM5 output 1 waveform to active or inactive level.
 *
 * @param   TIM_ForcedAction - specifies the forced Action to be set to the
 *        output waveform.
 *            TIM_ForcedAction_Active - Force active level on OC1REF.
 *            TIM_ForcedAction_InActive - Force inactive level on OC1REF.
 *
 * @return  none
 */
void TIM5_ForcedOC1Config(uint16_t TIM_ForcedAction)
{
    uint16_t tmpccmr1 = 0;

    tmpccmr1 = TIM5->CHCTLR1;
    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M);
    tmpccmr1 |= TIM_ForcedAction;
    TIM5->CHCTLR1 = tmpccmr1;
}

/*********************************************************************
 * @fn      TIM5_ForcedOC2Config
 *
 * @brief   Forces the TIM5 output 2 waveform to active or inactive level.
 *
 * @param   TIM_ForcedAction - specifies the forced Action to be set to the
 *        output waveform.
 *            TIM_ForcedAction_Active - Force active level on OC2REF.
 *            TIM_ForcedAction_InActive - Force inactive level on OC2REF.
 *
 * @return  none
 */
void TIM5_ForcedOC2Config(uint16_t TIM_ForcedAction)
{
    uint16_t tmpccmr1 = 0;

    tmpccmr1 = TIM5->CHCTLR1;
    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M);
    tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
    TIM5->CHCTLR1 = tmpccmr1;
}

/*********************************************************************
 * @fn      TIM5_ForcedOC3Config
 *
 * @brief   Forces the TIM5 output 3 waveform to active or inactive level.
 *
 * @param   TIM_ForcedAction - specifies the forced Action to be set to the
 *        output waveform.
 *            TIM_ForcedAction_Active - Force active level on OC3REF.
 *            TIM_ForcedAction_InActive - Force inactive level on OC3REF.
 *
 * @return  none
 */
void TIM5_ForcedOC3Config(uint16_t TIM_ForcedAction)
{
    uint16_t tmpccmr2 = 0;

    tmpccmr2 = TIM5->CHCTLR2;
    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M);
    tmpccmr2 |= TIM_ForcedAction;
    TIM5->CHCTLR2 = tmpccmr2;
}

/*********************************************************************
 * @fn      TIM5_ForcedOC4Config
 *
 * @brief   Forces the TIM5 output 4 waveform to active or inactive level.
 *
 * @param   TIM_ForcedAction - specifies the forced Action to be set to the
 *        output waveform.
 *            TIM_ForcedAction_Active - Force active level on OC4REF.
 *            TIM_ForcedAction_InActive - Force inactive level on OC4REF.
 *
 * @return  none
 */
void TIM5_ForcedOC4Config(uint16_t TIM_ForcedAction)
{
    uint16_t tmpccmr2 = 0;

    tmpccmr2 = TIM5->CHCTLR2;
    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M);
    tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
    TIM5->CHCTLR2 = tmpccmr2;
}

/*********************************************************************
 * @fn      TIM5_ARRPreloadConfig
 *
 * @brief   Enables or disables TIM5 peripheral Preload register on ARR.
 *
 * @param   NewState - ENABLE or DISABLE.
 *
 * @return  none
 */
void TIM5_ARRPreloadConfig(FunctionalState NewState)
{
    if(NewState != DISABLE)
    {
        TIM5->CTLR1 |= TIM_ARPE;
    }
    else
    {
        TIM5->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE);
    }
}

/*********************************************************************
 * @fn      TIM5_SelectCOM
 *
 * @brief   Selects the TIM peripheral Commutation event.
 *
 * @param   NewState - ENABLE or DISABLE.
 *
 * @return  none
 */
void TIM5_SelectCOM(FunctionalState NewState)
{
    if(NewState != DISABLE)
    {
        TIM5->CTLR2 |= TIM_CCUS;
    }
    else
    {
        TIM5->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS);
    }
}

/*********************************************************************
 * @fn      TIM5_SelectCCDMA
 *
 * @brief   Selects the TIM5 peripheral Capture Compare DMA source.
 *
 * @param   NewState - ENABLE or DISABLE.
 *
 * @return  none
 */
void TIM5_SelectCCDMA(FunctionalState NewState)
{
    if(NewState != DISABLE)
    {
        TIM5->CTLR2 |= TIM_CCDS;
    }
    else
    {
        TIM5->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS);
    }
}

/*********************************************************************
 * @fn      TIM5_CCPreloadControl
 *
 * @brief   DSets or Resets the TIM peripheral Capture Compare Preload Control bit.
 *        reset values (Affects also the I2Ss).
 * @param   NewState - ENABLE or DISABLE.
 *
 * @return  none
 */
void TIM5_CCPreloadControl(FunctionalState NewState)
{
    if(NewState != DISABLE)
    {
        TIM5->CTLR2 |= TIM_CCPC;
    }
    else
    {
        TIM5->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC);
    }
}

/*********************************************************************
 * @fn      TIM5_OC1PreloadConfig
 *
 * @brief   Enables or disables the TIM5 peripheral Preload register on CCR1.
 *
 * @param   TIM_OCPreload - new state of the TIM5 peripheral Preload register.
 *            TIM_OCPreload_Enable.
 *            TIM_OCPreload_Disable.
 *
 * @return  none
 */
void TIM5_OC1PreloadConfig(uint16_t TIM_OCPreload)
{
    uint16_t tmpccmr1 = 0;

    tmpccmr1 = TIM5->CHCTLR1;
    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE);
    tmpccmr1 |= TIM_OCPreload;
    TIM5->CHCTLR1 = tmpccmr1;
}

/*********************************************************************
 * @fn      TIM5_OC2PreloadConfig
 *
 * @brief   Enables or disables the TIM5 peripheral Preload register on CCR2.
 *
 * @param   TIM_OCPreload - new state of the TIM5 peripheral Preload register.
 *            TIM_OCPreload_Enable.
 *            TIM_OCPreload_Disable.
 *
 * @return  none
 */
void TIM5_OC2PreloadConfig(uint16_t TIM_OCPreload)
{
    uint16_t tmpccmr1 = 0;

    tmpccmr1 = TIM5->CHCTLR1;
    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE);
    tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
    TIM5->CHCTLR1 = tmpccmr1;
}

/*********************************************************************
 * @fn      TIM5_OC3PreloadConfig
 *
 * @brief   Enables or disables the TIM5 peripheral Preload register on CCR3.
 *
 * @param   TIM_OCPreload - new state of the TIM5 peripheral Preload register.
 *            TIM_OCPreload_Enable.
 *            TIM_OCPreload_Disable.
 *
 * @return  none
 */
void TIM5_OC3PreloadConfig(uint16_t TIM_OCPreload)
{
    uint16_t tmpccmr2 = 0;

    tmpccmr2 = TIM5->CHCTLR2;
    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE);
    tmpccmr2 |= TIM_OCPreload;
    TIM5->CHCTLR2 = tmpccmr2;
}

/*********************************************************************
 * @fn      TIM5_OC4PreloadConfig
 *
 * @brief   Enables or disables the TIM5 peripheral Preload register on CCR4.
 *
 * @param   TIM_OCPreload - new state of the TIM5 peripheral Preload register.
 *            TIM_OCPreload_Enable.
 *            TIM_OCPreload_Disable.
 *
 * @return  none
 */
void TIM5_OC4PreloadConfig(uint16_t TIM_OCPreload)
{
    uint16_t tmpccmr2 = 0;

    tmpccmr2 = TIM5->CHCTLR2;
    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE);
    tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
    TIM5->CHCTLR2 = tmpccmr2;
}

/*********************************************************************
 * @fn      TIM5_OC1FastConfig
 *
 * @brief   Configures the TIM5 Output Compare 1 Fast feature.
 *
 * @param   TIM_OCFast - new state of the Output Compare Fast Enable Bit.
 *            TIM_OCFast_Enable - TIM output compare fast enable.
 *            TIM_OCFast_Disable - TIM output compare fast disable.
 *
 * @return  none
 */
void TIM5_OC1FastConfig(uint16_t TIM_OCFast)
{
    uint16_t tmpccmr1 = 0;

    tmpccmr1 = TIM5->CHCTLR1;
    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE);
    tmpccmr1 |= TIM_OCFast;
    TIM5->CHCTLR1 = tmpccmr1;
}

/*********************************************************************
 * @fn      TIM5_OC2FastConfig
 *
 * @brief   Configures the TIM5 Output Compare 2 Fast feature.
 *
 * @param   TIM_OCFast - new state of the Output Compare Fast Enable Bit.
 *            TIM_OCFast_Enable - TIM output compare fast enable.
 *            TIM_OCFast_Disable - TIM output compare fast disable.
 *
 * @return  none
 */
void TIM5_OC2FastConfig(uint16_t TIM_OCFast)
{
    uint16_t tmpccmr1 = 0;

    tmpccmr1 = TIM5->CHCTLR1;
    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE);
    tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
    TIM5->CHCTLR1 = tmpccmr1;
}

/*********************************************************************
 * @fn      TIM5_OC3FastConfig
 *
 * @brief   Configures the TIM5 Output Compare 3 Fast feature.
 *
 * @param   TIM5 - where x can be 1 to 4 to select the TIM peripheral.
 *          TIM_OCFast - new state of the Output Compare Fast Enable Bit.
 *            TIM_OCFast_Enable - TIM output compare fast enable.
 *            TIM_OCFast_Disable - TIM output compare fast disable.
 *
 * @return  none
 */
void TIM5_OC3FastConfig(uint16_t TIM_OCFast)
{
    uint16_t tmpccmr2 = 0;

    tmpccmr2 = TIM5->CHCTLR2;
    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE);
    tmpccmr2 |= TIM_OCFast;
    TIM5->CHCTLR2 = tmpccmr2;
}

/*********************************************************************
 * @fn      TIM5_OC4FastConfig
 *
 * @brief   Configures the TIM5 Output Compare 4 Fast feature.
 *
 * @param   TIM_OCFast - new state of the Output Compare Fast Enable Bit.
 *            TIM_OCFast_Enable - TIM output compare fast enable.
 *            TIM_OCFast_Disable - TIM output compare fast disable.
 *
 * @return  none
 */
void TIM5_OC4FastConfig(uint16_t TIM_OCFast)
{
    uint16_t tmpccmr2 = 0;

    tmpccmr2 = TIM5->CHCTLR2;
    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE);
    tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
    TIM5->CHCTLR2 = tmpccmr2;
}

/*********************************************************************
 * @fn      TIM5_ClearOC1Ref
 *
 * @brief   Clears or safeguards the OCREF1 signal on an external event.
 *
 * @param   TIM_OCClear - new state of the Output Compare Clear Enable Bit.
 *            TIM_OCClear_Enable - TIM Output clear enable.
 *            TIM_OCClear_Disable - TIM Output clear disable.
 *
 * @return  none
 */
void TIM5_ClearOC1Ref(uint16_t TIM_OCClear)
{
    uint16_t tmpccmr1 = 0;

    tmpccmr1 = TIM5->CHCTLR1;
    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE);
    tmpccmr1 |= TIM_OCClear;
    TIM5->CHCTLR1 = tmpccmr1;
}

/*********************************************************************
 * @fn      TIM5_ClearOC2Ref
 *
 * @brief   Clears or safeguards the OCREF2 signal on an external event.
 *
 * @param   TIM_OCClear - new state of the Output Compare Clear Enable Bit.
 *            TIM_OCClear_Enable - TIM Output clear enable.
 *            TIM_OCClear_Disable - TIM Output clear disable.
 *
 * @return  none
 */
void TIM5_ClearOC2Ref(uint16_t TIM_OCClear)
{
    uint16_t tmpccmr1 = 0;

    tmpccmr1 = TIM5->CHCTLR1;
    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE);
    tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
    TIM5->CHCTLR1 = tmpccmr1;
}

/*********************************************************************
 * @fn      TIM5_ClearOC3Ref
 *
 * @brief   Clears or safeguards the OCREF3 signal on an external event.
 *
 * @param   TIM_OCClear - new state of the Output Compare Clear Enable Bit.
 *            TIM_OCClear_Enable - TIM Output clear enable.
 *            TIM_OCClear_Disable - TIM Output clear disable.
 *
 * @return  none
 */
void TIM5_ClearOC3Ref(uint16_t TIM_OCClear)
{
    uint16_t tmpccmr2 = 0;

    tmpccmr2 = TIM5->CHCTLR2;
    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE);
    tmpccmr2 |= TIM_OCClear;
    TIM5->CHCTLR2 = tmpccmr2;
}

/*********************************************************************
 * @fn      TIM5_ClearOC4Ref
 *
 * @brief   Clears or safeguards the OCREF4 signal on an external event.
 *
 * @param   TIM_OCClear - new state of the Output Compare Clear Enable Bit.
 *            TIM_OCClear_Enable - TIM Output clear enable.
 *            TIM_OCClear_Disable - TIM Output clear disable.
 *
 * @return  none
 */
void TIM5_ClearOC4Ref(uint16_t TIM_OCClear)
{
    uint16_t tmpccmr2 = 0;

    tmpccmr2 = TIM5->CHCTLR2;
    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE);
    tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
    TIM5->CHCTLR2 = tmpccmr2;
}

/*********************************************************************
 * @fn      TIM5_OC1PolarityConfig
 *
 * @brief   Configures the TIM5 channel 1 polarity.
 *
 * @param   TIM_OCPolarity - specifies the OC1 Polarity.
 *            TIM_OCPolarity_High - Output Compare active high.
 *            TIM_OCPolarity_Low - Output Compare active low.
 *
 * @return  none
 */
void TIM5_OC1PolarityConfig(uint16_t TIM_OCPolarity)
{
    uint16_t tmpccer = 0;

    tmpccer = TIM5->CCER;
    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P);
    tmpccer |= TIM_OCPolarity;
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TIM5_OC1NPolarityConfig
 *
 * @brief   Configures the TIM5 channel 1 polarity.
 *
 * @param   TIM_OCNPolarity - specifies the OC1N Polarity.
 *            TIM_OCNPolarity_High - Output Compare active high.
 *            TIM_OCNPolarity_Low - Output Compare active low.
 *
 * @return  none
 */
void TIM5_OC1NPolarityConfig(uint16_t TIM_OCNPolarity)
{
    uint16_t tmpccer = 0;

    tmpccer = TIM5->CCER;
    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP);
    tmpccer |= TIM_OCNPolarity;
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TIM5_OC2PolarityConfig
 *
 * @brief   Configures the TIM5 channel 2 polarity.
 *
 * @param   TIM_OCPolarity - specifies the OC2 Polarity.
 *            TIM_OCPolarity_High - Output Compare active high.
 *            TIM_OCPolarity_Low - Output Compare active low.
 *
 * @return  none
 */
void TIM5_OC2PolarityConfig(uint16_t TIM_OCPolarity)
{
    uint16_t tmpccer = 0;

    tmpccer = TIM5->CCER;
    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P);
    tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TIM5_OC2NPolarityConfig
 *
 * @brief   Configures the TIM5 channel 2 polarity.
 *
 * @param   TIM_OCNPolarity - specifies the OC1N Polarity.
 *            TIM_OCNPolarity_High - Output Compare active high.
 *            TIM_OCNPolarity_Low - Output Compare active low.
 *
 * @return  none
 */
void TIM5_OC2NPolarityConfig(uint16_t TIM_OCNPolarity)
{
    uint16_t tmpccer = 0;

    tmpccer = TIM5->CCER;
    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP);
    tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TIM5_OC3PolarityConfig
 *
 * @brief   Configures the TIM5 Channel 3 polarity.
 *
 * @param   TIM_OCPolarit - specifies the OC3 Polarity.
 *            TIM_OCPolarity_High - Output Compare active high.
 *            TIM_OCPolarity_Low - Output Compare active low.
 *
 * @return  none
 */
void TIM5_OC3PolarityConfig(uint16_t TIM_OCPolarity)
{
    uint16_t tmpccer = 0;

    tmpccer = TIM5->CCER;
    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P);
    tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TIM5_OC3NPolarityConfig
 *
 * @brief   Configures the TIM5 Channel 3N polarity.
 *
 * @param   TIM_OCNPolarity - specifies the OC2N Polarity.
 *            TIM_OCNPolarity_High - Output Compare active high.
 *            TIM_OCNPolarity_Low - Output Compare active low.
 *
 * @return  none
 */
void TIM5_OC3NPolarityConfig(uint16_t TIM_OCNPolarity)
{
    uint16_t tmpccer = 0;

    tmpccer = TIM5->CCER;
    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP);
    tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TIM5_OC4PolarityConfig
 *
 * @brief   Configures the TIM5 Channel 4 polarity.
 *
 * @param   TIM_OCPolarit - specifies the OC3 Polarity.
 *            TIM_OCPolarity_High - Output Compare active high.
 *            TIM_OCPolarity_Low - Output Compare active low.
 *
 * @return  none
 */
void TIM5_OC4PolarityConfig(uint16_t TIM_OCPolarity)
{
    uint16_t tmpccer = 0;

    tmpccer = TIM5->CCER;
    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P);
    tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TIM5_CCxCmd
 *
 * @brief   Enables or disables the TIM Capture Compare Channel x.
 *
 * @param   TIM_Channel - specifies the TIM Channel.
 *            TIM_Channel_1 - TIM Channel 1.
 *            TIM_Channel_2 - TIM Channel 2.
 *            TIM_Channel_3 - TIM Channel 3.
 *            TIM_Channel_4 - TIM Channel 4.
 *          TIM_CCx - specifies the TIM Channel CCxE bit new state.
 *            TIM_CCx_Enable.
 *            TIM_CCx_Disable.
 *
 * @return  none
 */
void TIM5_CCxCmd(uint16_t TIM_Channel, uint16_t TIM_CCx)
{
    uint16_t tmp = 0;

    tmp = TIM5_CCER_CCE_Set << TIM_Channel;
    TIM5->CCER &= (uint16_t)~tmp;
    TIM5->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
}

/*********************************************************************
 * @fn      TIM5_CCxNCmd
 *
 * @brief   Enables or disables the TIM Capture Compare Channel xN.
 *
 * @param   TIM_Channel - specifies the TIM Channel.
 *            TIM_Channel_1 - TIM Channel 1.
 *            TIM_Channel_2 - TIM Channel 2.
 *            TIM_Channel_3 - TIM Channel 3.
 *          TIM_CCxN - specifies the TIM Channel CCxNE bit new state.
 *            TIM_CCxN_Enable.
 *            TIM_CCxN_Disable.
 *
 * @return  none
 */
void TIM5_CCxNCmd(uint16_t TIM_Channel, uint16_t TIM_CCxN)
{
    uint16_t tmp = 0;

    tmp = TIM5_CCER_CCNE_Set << TIM_Channel;
    TIM5->CCER &= (uint16_t)~tmp;
    TIM5->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
}

/*********************************************************************
 * @fn      TIM5_SelectOCxM
 *
 * @brief   Selects the TIM Output Compare Mode.
 *
 * @param   TIM_Channel - specifies the TIM Channel.
 *            TIM_Channel_1 - TIM Channel 1.
 *            TIM_Channel_2 - TIM Channel 2.
 *            TIM_Channel_3 - TIM Channel 3.
 *            TIM_Channel_4 - TIM Channel 4.
 *          TIM_OCMode - specifies the TIM Output Compare Mode.
 *            TIM_OCMode_Timing.
 *            TIM_OCMode_Active.
 *            TIM_OCMode_Toggle.
 *            TIM_OCMode_PWM1.
 *            TIM_OCMode_PWM2.
 *            TIM_ForcedAction_Active.
 *            TIM_ForcedAction_InActive.
 *
 * @return  none
 */
void TIM5_SelectOCxM(uint16_t TIM_Channel, uint16_t TIM_OCMode)
{
    uint32_t tmp = 0;
    uint16_t tmp1 = 0;

    tmp = (uint32_t)TIM5;
    tmp += TIM5_CHCTLR_Offset;
    tmp1 = TIM5_CCER_CCE_Set << (uint16_t)TIM_Channel;
    TIM5->CCER &= (uint16_t)~tmp1;

    if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3))
    {
        tmp += (TIM_Channel >> 1);
        *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M);
        *(__IO uint32_t *)tmp |= TIM_OCMode;
    }
    else
    {
        tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1;
        *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M);
        *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8);
    }
}

/*********************************************************************
 * @fn      TIM5_UpdateDisableConfig
 *
 * @brief   Enables or Disables the TIM5 Update event.
 *
 * @param   NewState - ENABLE or DISABLE.
 *
 * @return  none
 */
void TIM5_UpdateDisableConfig(FunctionalState NewState)
{
    if(NewState != DISABLE)
    {
        TIM5->CTLR1 |= TIM_UDIS;
    }
    else
    {
        TIM5->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS);
    }
}

/*********************************************************************
 * @fn      TIM5_UpdateRequestConfig
 *
 * @brief   Configures the TIM5 Update Request Interrupt source.
 *
 * @param   TIM_UpdateSource - specifies the Update source.
 *            TIM_UpdateSource_Regular.
 *            TIM_UpdateSource_Global.
 *
 * @return  none
 */
void TIM5_UpdateRequestConfig(uint16_t TIM_UpdateSource)
{
    if(TIM_UpdateSource != TIM_UpdateSource_Global)
    {
        TIM5->CTLR1 |= TIM_URS;
    }
    else
    {
        TIM5->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS);
    }
}

/*********************************************************************
 * @fn      TIM5_SelectHallSensor
 *
 * @brief   Enables or disables the TIM5's Hall sensor interface.
 *
 * @param   NewState - ENABLE or DISABLE.
 *
 * @return  none
 */
void TIM5_SelectHallSensor(FunctionalState NewState)
{
    if(NewState != DISABLE)
    {
        TIM5->CTLR2 |= TIM_TI1S;
    }
    else
    {
        TIM5->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S);
    }
}

/*********************************************************************
 * @fn      TIM5_SelectOnePulseMode
 *
 * @brief   Selects the TIM5's One Pulse Mode.
 *
 * @param   TIM_OPMode - specifies the OPM Mode to be used.
 *            TIM_OPMode_Single.
 *            TIM_OPMode_Repetitive.
 *
 * @return  none
 */
void TIM5_SelectOnePulseMode(uint16_t TIM_OPMode)
{
    TIM5->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM);
    TIM5->CTLR1 |= TIM_OPMode;
}

/*********************************************************************
 * @fn      TIM5_SelectOutputTrigger
 *
 * @brief   Selects the TIM5 Trigger Output Mode.
 *
 * @param   TIM_TRGOSource - specifies the Trigger Output source.
 *            TIM_TRGOSource_Reset -  The UG bit in the TIM_EGR register is
 *        used as the trigger output (TRGO).
 *            TIM_TRGOSource_Enable - The Counter Enable CEN is used as the
 *        trigger output (TRGO).
 *            TIM_TRGOSource_Update - The update event is selected as the
 *        trigger output (TRGO).
 *            TIM_TRGOSource_OC1 - The trigger output sends a positive pulse
 *        when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO).
 *            TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO).
 *            TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO).
 *            TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO).
 *            TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO).
 *
 * @return  none
 */
void TIM5_SelectOutputTrigger(uint16_t TIM_TRGOSource)
{
    TIM5->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS);
    TIM5->CTLR2 |= TIM_TRGOSource;
}

/*********************************************************************
 * @fn      TIM5_SelectSlaveMode
 *
 * @brief   Selects the TIM5 Slave Mode.
 *
 * @param   TIM_SlaveMode - specifies the Timer Slave Mode.
 *            TIM_SlaveMode_Reset - Rising edge of the selected trigger
 *        signal (TRGI) re-initializes.
 *            TIM_SlaveMode_Gated - The counter clock is enabled when the
 *        trigger signal (TRGI) is high.
 *            TIM_SlaveMode_Trigger - The counter starts at a rising edge
 *        of the trigger TRGI.
 *            TIM_SlaveMode_External1 - Rising edges of the selected trigger
 *        (TRGI) clock the counter.
 *
 * @return  none
 */
void TIM5_SelectSlaveMode(uint16_t TIM_SlaveMode)
{
    TIM5->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS);
    TIM5->SMCFGR |= TIM_SlaveMode;
}

/*********************************************************************
 * @fn      TIM5_SelectMasterSlaveMode
 *
 * @brief   Sets or Resets the TIM5 Master/Slave Mode.
 *
 * @param   TIM_MasterSlaveMode - specifies the Timer Master Slave Mode.
 *            TIM_MasterSlaveMode_Enable - synchronization between the current
 *        timer and its slaves (through TRGO).
 *            TIM_MasterSlaveMode_Disable - No action.
 *
 * @return  none
 */
void TIM5_SelectMasterSlaveMode(uint16_t TIM_MasterSlaveMode)
{
    TIM5->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM);
    TIM5->SMCFGR |= TIM_MasterSlaveMode;
}

/*********************************************************************
 * @fn      TIM_SetCounter
 *
 * @brief   Sets the TIM5 Counter Register value.
 *
 * @param   Counter - specifies the Counter register new value.
 *
 * @return  none
 */
void TIM5_SetCounter(uint32_t Counter)
{
    TIM5->CNT_R32 = Counter;
}

/*********************************************************************
 * @fn      TIM5_SetAutoreload
 *
 * @brief   Sets the TIM5 Autoreload Register value.
 *
 * @param   Autoreload - specifies the Autoreload register new value.
 *
 * @return  none
 */
void TIM5_SetAutoreload(uint32_t Autoreload)
{
    TIM5->ATRLR_R32 = Autoreload;
}

/*********************************************************************
 * @fn      TIM5_SetCompare1
 *
 * @brief   Sets the TIM5 Capture Compare1 Register value.
 *
 * @param   Compare1 - specifies the Capture Compare1 register new value.
 *
 * @return  none
 */
void TIM5_SetCompare1(uint32_t Compare1)
{
    TIM5->CH1CVR_R32 = Compare1;
}

/*********************************************************************
 * @fn      TIM5_SetCompare2
 *
 * @brief   Sets the TIM5 Capture Compare2 Register value.
 *
 * @param   Compare1 - specifies the Capture Compare1 register new value.
 *
 * @return  none
 */
void TIM5_SetCompare2(uint32_t Compare2)
{
    TIM5->CH2CVR_R32 = Compare2;
}

/*********************************************************************
 * @fn      TIM5_SetCompare3
 *
 * @brief   Sets the TIM5 Capture Compare3 Register value.
 *
 * @param   Compare1 - specifies the Capture Compare1 register new value.
 *
 * @return  none
 */
void TIM5_SetCompare3(uint32_t Compare3)
{
    TIM5->CH3CVR_R32 = Compare3;
}

/*********************************************************************
 * @fn      TIM5_SetCompare4
 *
 * @brief   Sets the TIM5 Capture Compare4 Register value.
 *
 * @param   Compare1 - specifies the Capture Compare1 register new value.
 *
 * @return  none
 */
void TIM5_SetCompare4(uint32_t Compare4)
{
    TIM5->CH4CVR_R32 = Compare4;
}

/*********************************************************************
 * @fn      TIM5_SetIC1Prescaler
 *
 * @brief   Sets the TIM5 Input Capture 1 prescaler.
 *
 * @param   TIM_ICPSC - specifies the Input Capture1 prescaler new value.
 *            TIM_ICPSC_DIV1 - no prescaler.
 *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
 *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
 *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
 *
 * @return  none
 */
void TIM5_SetIC1Prescaler(uint16_t TIM_ICPSC)
{
    TIM5->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC);
    TIM5->CHCTLR1 |= TIM_ICPSC;
}

/*********************************************************************
 * @fn      TIM5_SetIC2Prescaler
 *
 * @brief   Sets the TIM5 Input Capture 2 prescaler.
 *
 * @param   TIM_ICPSC - specifies the Input Capture1 prescaler new value.
 *            TIM_ICPSC_DIV1 - no prescaler.
 *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
 *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
 *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
 *
 * @return  none
 */
void TIM5_SetIC2Prescaler(uint16_t TIM_ICPSC)
{
    TIM5->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC);
    TIM5->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8);
}

/*********************************************************************
 * @fn      TIM5_SetIC3Prescaler
 *
 * @brief   Sets the TIM5 Input Capture 3 prescaler.
 *
 * @param   TIM_ICPSC - specifies the Input Capture1 prescaler new value.
 *            TIM_ICPSC_DIV1 - no prescaler.
 *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
 *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
 *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
 *
 * @return  none
 */
void TIM5_SetIC3Prescaler(uint16_t TIM_ICPSC)
{
    TIM5->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC);
    TIM5->CHCTLR2 |= TIM_ICPSC;
}

/*********************************************************************
 * @fn      TIM5_SetIC4Prescaler
 *
 * @brief   Sets the TIM5 Input Capture 4 prescaler.
 *
 * @param   TIM_ICPSC - specifies the Input Capture1 prescaler new value.
 *            TIM_ICPSC_DIV1 - no prescaler.
 *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
 *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
 *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
 *
 * @return  none
 */
void TIM5_SetIC4Prescaler(uint16_t TIM_ICPSC)
{
    TIM5->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC);
    TIM5->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8);
}

/*********************************************************************
 * @fn      TIM5_SetClockDivision
 *
 * @brief   Sets the TIM5 Clock Division value.
 *
 * @param   TIM_CKD - specifies the clock division value.
 *            TIM_CKD_DIV1 - TDTS = Tck_tim.
 *            TIM_CKD_DIV2 - TDTS = 2*Tck_tim.
 *            TIM_CKD_DIV4 - TDTS = 4*Tck_tim.
 *
 * @return  none
 */
void TIM5_SetClockDivision(uint16_t TIM_CKD)
{
    TIM5->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD);
    TIM5->CTLR1 |= TIM_CKD;
}

/*********************************************************************
 * @fn      TIM_GetCapture1
 *
 * @brief   Gets the TIM5 Input Capture 1 value.
 *
 * @param   none
 *
 * @return  TIM5->CH1CVR - Capture Compare 1 Register value.
 */
uint32_t TIM5_GetCapture1(void)
{
    return TIM5->CH1CVR_R32;
}

/*********************************************************************
 * @fn      TIM_GetCapture2
 *
 * @brief   Gets the TIM5 Input Capture 2 value.
 *
 * @param   none
 *
 * @return  TIM5->CH2CVR - Capture Compare 2 Register value.
 */
uint32_t TIM5_GetCapture2(void)
{
    return TIM5->CH2CVR_R32;
}

/*********************************************************************
 * @fn      TIM_GetCapture3
 *
 * @brief   Gets the TIM5 Input Capture 3 value.
 *
 * @param   none
 *
 * @return  TIM5->CH3CVR - Capture Compare 3 Register value.
 */
uint32_t TIM5_GetCapture3(void)
{
    return TIM5->CH3CVR_R32;
}

/*********************************************************************
 * @fn      TIM_GetCapture4
 *
 * @brief   Gets the TIM5 Input Capture 4 value.
 *
 * @param   none
 *
 * @return  TIM5->CH4CVR - Capture Compare 4 Register value.
 */
uint32_t TIM5_GetCapture4(void)
{
    return TIM5->CH4CVR_R32;
}

/*********************************************************************
 * @fn      TIM_GetCounter
 *
 * @brief   Gets the TIM5 Counter value.
 *
 * @param   none
 *
 * @return  TIM5->CNT_R32 - Counter Register value.
 */
uint32_t TIM5_GetCounter(void)
{
    return TIM5->CNT_R32;
}

/*********************************************************************
 * @fn      TIM_GetPrescaler
 *
 * @brief   Gets the TIM5 Prescaler value.
 *
 * @param   none
 *
 * @return  TIM5->PSC - Prescaler Register value.
 */
uint16_t TIM5_GetPrescaler(void)
{
    return TIM5->PSC;
}

/*********************************************************************
 * @fn      TIM5_GetFlagStatus
 *
 * @brief   Checks whether the specified TIM flag is set or not.
 *
 * @param   TIM_FLAG - specifies the flag to check.
 *            TIM_FLAG_Update - TIM update Flag.
 *            TIM_FLAG_CC1 - TIM Capture Compare 1 Flag.
 *            TIM_FLAG_CC2 - TIM Capture Compare 2 Flag.
 *            TIM_FLAG_CC3 - TIM Capture Compare 3 Flag.
 *            TIM_FLAG_CC4 - TIM Capture Compare 4 Flag.
 *            TIM_FLAG_COM - TIM Commutation Flag.
 *            TIM_FLAG_Trigger - TIM Trigger Flag.
 *            TIM_FLAG_Break - TIM Break Flag.
 *            TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag.
 *            TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag.
 *            TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag.
 *            TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag.
 *
 * @return  none
 */
FlagStatus TIM5_GetFlagStatus(uint16_t TIM_FLAG)
{
    ITStatus bitstatus = RESET;

    if((TIM5->INTFR & TIM_FLAG) != (uint16_t)RESET)
    {
        bitstatus = SET;
    }
    else
    {
        bitstatus = RESET;
    }

    return bitstatus;
}

/*********************************************************************
 * @fn      TIM5_ClearFlag
 *
 * @brief   Clears the TIM5's pending flags.
 *
 * @param   TIM_FLAG - specifies the flag to check.
 *            TIM_FLAG_Update - TIM update Flag.
 *            TIM_FLAG_CC1 - TIM Capture Compare 1 Flag.
 *            TIM_FLAG_CC2 - TIM Capture Compare 2 Flag.
 *            TIM_FLAG_CC3 - TIM Capture Compare 3 Flag.
 *            TIM_FLAG_CC4 - TIM Capture Compare 4 Flag.
 *            TIM_FLAG_COM - TIM Commutation Flag.
 *            TIM_FLAG_Trigger - TIM Trigger Flag.
 *            TIM_FLAG_Break - TIM Break Flag.
 *            TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag.
 *            TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag.
 *            TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag.
 *            TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag.
 *
 * @return  none
 */
void TIM5_ClearFlag(uint16_t TIM_FLAG)
{
    TIM5->INTFR = (uint16_t)~TIM_FLAG;
}

/*********************************************************************
 * @fn      TIM5_GetITStatus
 *
 * @brief   Checks whether the TIM interrupt has occurred or not.
 *
 * @param   TIM_IT - specifies the TIM interrupt source to check.
 *            TIM_IT_Update - TIM update Interrupt source.
 *            TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source.
 *            TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source.
 *            TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source.
 *            TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source.
 *            TIM_IT_COM - TIM Commutation Interrupt source.
 *            TIM_IT_Trigger - TIM Trigger Interrupt source.
 *            TIM_IT_Break - TIM Break Interrupt source.
 *
 * @return  none
 */
ITStatus TIM5_GetITStatus(uint16_t TIM_IT)
{
    ITStatus bitstatus = RESET;
    uint16_t itstatus = 0x0, itenable = 0x0;

    itstatus = TIM5->INTFR & TIM_IT;

    itenable = TIM5->DMAINTENR & TIM_IT;
    if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
    {
        bitstatus = SET;
    }
    else
    {
        bitstatus = RESET;
    }

    return bitstatus;
}

/*********************************************************************
 * @fn      TIM5_ClearITPendingBit
 *
 * @brief   Clears the TIM5's interrupt pending bits.
 *
 * @param   TIM_IT - specifies the TIM interrupt source to check.
 *            TIM_IT_Update - TIM update Interrupt source.
 *            TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source.
 *            TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source.
 *            TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source.
 *            TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source.
 *            TIM_IT_COM - TIM Commutation Interrupt source.
 *            TIM_IT_Trigger - TIM Trigger Interrupt source.
 *            TIM_IT_Break - TIM Break Interrupt source.
 *
 * @return  none
 */
void TIM5_ClearITPendingBit(uint16_t TIM_IT)
{
    TIM5->INTFR = (uint16_t)~TIM_IT;
}

/*********************************************************************
 * @fn      TI1_Config
 *
 * @brief   Configure the TI1 as Input.
 *
 * @param   IM_ICPolarity - The Input Polarity.
 *             TIM_ICPolarity_Rising.
 *             TIM_ICPolarity_Falling.
 *          TIM_ICSelection - specifies the input to be used.
 *             TIM_ICSelection_DirectTI - TIM Input 1 is selected to be
 *        connected to IC1.
 *             TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be
 *        connected to IC2.
 *             TIM_ICSelection_TRC - TIM Input 1 is selected to be connected
 *        to TRC.
 *          TIM_ICFilter - Specifies the Input Capture Filter.
 *            This parameter must be a value between 0x00 and 0x0F.
 *
 * @return  none
 */
static void TI1_Config(uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
{
    uint16_t tmpccmr1 = 0, tmpccer = 0;

    TIM5->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E);
    tmpccmr1 = TIM5->CHCTLR1;
    tmpccer = TIM5->CCER;
    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F)));
    tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));

    tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P));
    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E);

    TIM5->CHCTLR1 = tmpccmr1;
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TI2_Config
 *
 * @brief   Configure the TI2 as Input.
 *
 * @param   IM_ICPolarity - The Input Polarity.
 *             TIM_ICPolarity_Rising.
 *             TIM_ICPolarity_Falling.
 *          TIM_ICSelection - specifies the input to be used.
 *             TIM_ICSelection_DirectTI - TIM Input 1 is selected to be
 *        connected to IC1.
 *             TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be
 *        connected to IC2.
 *             TIM_ICSelection_TRC - TIM Input 1 is selected to be connected
 *        to TRC.
 *          TIM_ICFilter - Specifies the Input Capture Filter.
 *            This parameter must be a value between 0x00 and 0x0F.
 *
 * @return  none
 */
static void TI2_Config(uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
{
    uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;

    TIM5->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E);
    tmpccmr1 = TIM5->CHCTLR1;
    tmpccer = TIM5->CCER;
    tmp = (uint16_t)(TIM_ICPolarity << 4);
    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F)));
    tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
    tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);

    tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P));
    tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E);

    TIM5->CHCTLR1 = tmpccmr1;
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TI3_Config
 *
 * @brief   Configure the TI3 as Input.
 *
 * @param   IM_ICPolarity - The Input Polarity.
 *             TIM_ICPolarity_Rising.
 *             TIM_ICPolarity_Falling.
 *          TIM_ICSelection - specifies the input to be used.
 *             TIM_ICSelection_DirectTI - TIM Input 1 is selected to be
 *        connected to IC1.
 *             TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be
 *        connected to IC2.
 *             TIM_ICSelection_TRC - TIM Input 1 is selected to be connected
 *        to TRC.
 *          TIM_ICFilter - Specifies the Input Capture Filter.
 *            This parameter must be a value between 0x00 and 0x0F.
 *
 * @return  none
 */
static void TI3_Config(uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
{
    uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;

    TIM5->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E);
    tmpccmr2 = TIM5->CHCTLR2;
    tmpccer = TIM5->CCER;
    tmp = (uint16_t)(TIM_ICPolarity << 8);
    tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F)));
    tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));

    tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P));
    tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E);

    TIM5->CHCTLR2 = tmpccmr2;
    TIM5->CCER = tmpccer;
}

/*********************************************************************
 * @fn      TI4_Config
 *
 * @brief   Configure the TI4 as Input.
 *
 * @param   IM_ICPolarity - The Input Polarity.
 *             TIM_ICPolarity_Rising.
 *             TIM_ICPolarity_Falling.
 *          TIM_ICSelection - specifies the input to be used.
 *             TIM_ICSelection_DirectTI - TIM Input 1 is selected to be
 *        connected to IC1.
 *             TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be
 *        connected to IC2.
 *             TIM_ICSelection_TRC - TIM Input 1 is selected to be connected
 *        to TRC.
 *          TIM_ICFilter - Specifies the Input Capture Filter.
 *            This parameter must be a value between 0x00 and 0x0F.
 *
 * @return  none
 */
static void TI4_Config(uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
{
    uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;

    TIM5->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E);
    tmpccmr2 = TIM5->CHCTLR2;
    tmpccer = TIM5->CCER;
    tmp = (uint16_t)(TIM_ICPolarity << 12);
    tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F)));
    tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
    tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);

    tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P));
    tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E);

    TIM5->CHCTLR2 = tmpccmr2;
    TIM5->CCER = tmpccer;
}
